The present invention relates generally to reconfigurable computing systems, and more particularly to a method for performing a plurality of logic operations through programmable logic virtualization.
Logic circuits are commonly used to perform a multitude of functions in electronic products, such as pattern recognition, communication, compression/decompression, encryption, and network protocol processing. As the complexity of these functions increases, so does the size and cost of the logic circuits needed to perform them.
Programmable logic devices are well suited for many applications as they can be reprogrammed to perform several different tasks. Programmable logic devices commonly consist of an array of logic elements, and the connections and functions of the logic elements are programmable. Once built into a product, they are not typically reprogrammed. Also, although programmable logic devices are flexible, they still suffer from a scalability problem. As the complexity of the functions they are required to perform increases, the number of logic elements in the array must increase, thereby increasing the size and cost of the device. After a certain point, more than one device is typically required thereby further increasing size and cost.
A logic device for performing a plurality of logic functions by sharing limited logic resources over time is described. Multiple contexts are created to facilitate the resource sharing, and special registers are used to allow key data to persist between context switches.
In accordance with a first aspect of the invention, a method for performing a plurality of logic operations, is provided. The method comprises the steps of providing a first context number. The method further comprises the step of providing a set of configuration bits and selecting a first subset of the configuration bits based on the first context number. Still further, the method comprises providing a first operand combination and selecting a first member of the first subset of the configuration bits based on the first operand combination. Additionally, the method comprises storing the first member of the first subset of the configuration bits in a memory, wherein the first member of the first subset of the configuration bits is associated with the first context number.
In some preferred embodiments, the plurality of logic operations is partitioned into two or more contexts, wherein each context represents a portion of a logic circuit. In other preferred embodiments, the set of configuration bits represents a logic circuit, wherein the set of configuration bits represents a collection of possible outputs for a logic function. In still other preferred embodiments, the set of configuration bits may be provided by retrieving the bits from a memory.
In some embodiments, the first subset of the configuration bits represents a portion of a logic circuit and/or a collection of possible outputs for a logic function. In certain embodiments, the method further comprises the step of providing a second context number. In such an instance the second context number is associated with a representation of a portion of a logic circuit. In such an embodiment, some portion of the first operand combination may be provided by retrieving a stored member of a second subset of the configuration bits. Further, the second subset of the configuration bits represents a portion of a logic circuit and/or a collection of possible outputs for a logic function. Still further in such an instance, the stored member of the second subset of the configuration bits may represent an output of a logic function.
In other embodiments, the first operand combination is provided by selecting a second member of the first subset of the configuration bits based on a second operand combination. In such an instance, the second operand combination may be provided by retrieving a stored member of a subset of the configuration bits and/or the second operand combination may be provided by selecting a member of a subset of the configuration bits. Further, the second operand combination preferably represents a particular combination of inputs to a logic function and the second member of the first subset of the configuration bits preferably represents an output of a logic function. In some embodiments, the first operand combination represents a particular combination of inputs to a logic function. In other embodiments, the first member of the first subset of the configuration bits represents an output of a logic function.
In accordance with another aspect of the present invention, an apparatus for performing a plurality of logic operations is provided. The apparatus comprises a selector for selecting a subset of a set of configuration bits and for selecting a member of the subset of the configuration bits, wherein the subset of the set of configuration bits is selected based on a context number and the member of the subset of the configuration bits is selected based on an operand combination and a memory device for storing the set of configuration bits and for storing the member of the subset of the configuration bits.
In some preferred embodiments the selector comprises a multiplexer. In other embodiments the selector comprises a first multiplexer coupled to a second multiplexer. In certain embodiments the memory device comprises a static random access memory (SRAM) and/or a bank of registers.